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PIC18F46J11 FAMILY
DS39932D-page 40
2011 Microchip Technology Inc.
3.2.3
EXTERNAL CLOCK INPUT
The EC and ECPLL Oscillator modes require an
external clock source to be connected to the OSC1 pin.
There is no oscillator start-up time required after a
Power-on Reset (POR) or after an exit from Sleep
mode.
In the EC Oscillator mode, the oscillator frequency
divided-by-4 is available on the OSC2 pin. In the
ECPLL Oscillator mode, the PLL output divided-by-4 is
available on the OSC2 pin. This signal may be used for
test purposes or to synchronize other logic. Figure 3-3
displays the pin connections for the EC Oscillator
mode.
FIGURE 3-3:
EXTERNAL CLOCK INPUT
OPERATION (EC AND
ECPLL CONFIGURATION)
3.2.4
PLL FREQUENCY MULTIPLIER
A Phase Locked Loop (PLL) circuit is provided as an
option for users who want to use a lower frequency
oscillator circuit, or to clock the device up to its highest
rated frequency from a crystal oscillator. This may be
useful for customers who are concerned with EMI due
to high-frequency crystals, or users who require higher
clock speeds from an internal oscillator.
3.2.5
INTERNAL OSCILLATOR BLOCK
The PIC18F46J11 family devices include an internal
oscillator block which generates two different clock
signals; either can be used as the microcontroller’s
clock source. The internal oscillator may eliminate the
need for external oscillator circuits on the OSC1 and/or
OSC2 pins.
The main output (INTOSC) is an 8 MHz clock source
which can be used to directly drive the device clock. It
also drives the INTOSC postscaler, which can provide
a range of clock frequencies from 31 kHz to 8 MHz.
Additionally, the INTOSC may be used in conjunction
with the PLL to generate clock frequencies up to
32 MHz.
The other clock source is the internal RC oscillator
(INTRC), which provides a nominal 31 kHz output.
INTRC is enabled if it is selected as the device clock
source. It is also enabled automatically when any of the
following are enabled:
Power-up Timer
Fail-Safe Clock Monitor
Watchdog Timer
Two-Speed Start-up
These features are discussed in more detail in
Section 26.0 “Special Features of the CPU”
.
The clock source frequency (INTOSC direct, INTRC
direct or INTOSC postscaler) is selected by configuring
the IRCF bits of the OSCCON register (page 44).
OSC1/CLKI
OSC2/CLKO
FOSC/4
Clock from
Ext. System
PIC18F46J11
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